This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-044836, filed Feb. 23, 1999; and No. 11-044837, filed Feb. 23, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a clock signal generator circuit for generating an internal clock signal synchronizing with a clock signal inputted from the outside of a chip and a semiconductor integrated circuit with the clock signal generator circuit, and more particularly to a semiconductor integrated circuit that has an off-chip driver which outputs the chip internal data outside the chip and whose operation is controlled on the basis of the clock signal generated at the clock signal generator circuit.
In the I/O section of semiconductor integrated circuits, including a semiconductor memory, such as a DRAM, the data has recently been inputted and outputted in synchronization with both of the leading edge and trailing edge of an external clock signal. Such a method is known as Double Data Rate (DDR) method. The DDR method enables data to be inputted and outputted twice as fast as a method of inputting and outputting the data in synchronization with either the leading edge or trailing edge of an external clock signal.
In a DDR type semiconductor circuit, three types of internal clock signals are generated in a chip to input and output the data in synchronization with both of the leading edge and trailing edge of an external clock signal. They are an internal clock signal Tu synchronizing with the leading edge of the external clock signal, an internal clock signal Td synchronizing with the trailing edge of the external clock signal, and an internal clock signal Tw synchronizing with both of the leading edge and trailing edge of the external clock signal.
In addition, an off-chip driver (OCD) acting as a data output circuit is provided in the I/O section of the chip. To perform output control of data, it is necessary to generate the internal clock signals, taking into account the signal delay time in the OCD, when there is a large delay time between the time a data output control internal clock signal is inputted to the OCD and the time the OCD outputs the data. Specifically, when the delay time in the OCD is so large that it cannot be ignored, it is necessary to generate an internal clock signal used to control the operation of the CD, the delay time of the OCD earlier than usual.
Various types of clock signal generator circuits for generating an internal clock signal in synchronization with an external clock signal have been considered. Of them, a Synchronous Mirror Delay (SMD) system used in xe2x80x9cA 2.5-ns Clock Access 250-MHz 256-Mb SDRAM with a Synchronous Mirror Delayxe2x80x9d ISSCC Digest of technical papers, pp. 374-375, February 1996 by T. Saeki, et al., and a Synchronous Adjustable Delay (SAD) system, including Synchronous Traced Backward Delay (STBD), disclosed in U.S. Pat. No. 5,867,432, issued to Haruki Toda, have been widely used because of the higher synchronous speed and less power consumption. The contents of which are incorporated herein by reference in the entirely.
The principle of a SAD clock signal generator circuit disclosed in U.S. Pat. No. 5,867,432 will be explained.
FIG. 1 is a block diagram of a SAD signal generator circuit.
The SAD signal generator circuit comprises an input buffer 11, a delay monitor circuit 12, a forward delay array 14 including a plurality of delay circuits 13 cascade-connected in a multistage manner, a backward delay array 16 including a plurality of delay circuits 15 cascade-connected in a multistage manner as equal the number of delay circuits 13 in the forward delay array 14, a control circuit 17, and an output buffer 18 to which the output of the backward delay array 16 is inputted. The control circuit 17 has as many state holding circuits (control elements) as equal the number of delay circuits in each of the forward delay array 14 and backward delay array 16. In FIG. 1, the circuit composed of the forward delay array 14, backward delay array 16, and control circuit 17 is called a SAD circuit SAD.
FIG. 2 is a timing chart to help explain an example of the operation of the clock signal generator circuit shown in FIG. 1. Consider a case where an external clock signal CK with a period of xcfx84 is inputted to the input buffer 11. The external clock signal CK is shaped in waveform and amplified by the input buffer 11 and the resulting signal is outputted as a pulse signal CLK. If the delay time in the input buffer 11 is D1, the pulse signal CLK lags behind the external clock signal CK by D1. The pulse signal CLK is inputted to the delay monitor circuit 12 and the control circuit 17 of the SAD circuit SAD.
The delay monitor circuit 12 has a delay time of A (=D1+D2) equal to the sum of the delay time D1 in the input buffer 11 and the delay time D2 in the output buffer 18. Thus, as shown in FIG. 2, the pulse signal Din outputted from the delay monitor circuit 12 lags behind the pulse signal CLK outputted from the input buffer 11 by a period of A and is inputted as a signal Din to the forward delay array 14.
The forward delay array 14 is composed of delay circuits 13 cascade-connected in a multistage manner as described earlier. During the time until the pulse signal CLK in the next cycle is inputted to the control circuit 17, the signal Din is delayed sequentially by the multistage cascade-connected delay circuits 13. After the pulse signal CLK in the next cycle has been inputted to the control circuit 17, the backward delay array 16 delays the pulse signal CLK in the next cycle sequentially. On the basis of the state where the forward pulse signal propagates along the forward delay array 14, the control circuit 17 controls the operation of the backward delay array 16 in such a manner that the propagation time of the backward pulse signal becomes equal to that of the forward pulse signal. Thus, the pulse signal CLK in the next cycle is delayed for the time (xcfx84xe2x88x92A) by the backward delay array 16. The output Dout of the backward delay array 16 is delayed for the time D2 and the resulting signal is outputted as an internal clock signal CKxe2x80x2.
If the delay time from when the external clock signal CK is inputted until the internal clock signal CKxe2x80x2 is outputted is xcex94total, then xcex94total is expressed as:
xcex94total=D1+A+2(xcfx84xe2x88x92A)+D2 xe2x80x83xe2x80x83(1)
Since D1+D2=A, xcex94total is 2xcfx84 and the internal clock signal CKxe2x80x2 synchronize with the external clock CK, starting at the third clock in the external clock signal CK.
In the clock signal generator circuit of FIG. 1, when the number of delay circuits 15 in the backward delay array 16 is reduced to half the number of delay circuits 13 in the forward delay array 14 so that the delay time in the backward delay array 16 may be half the delay time in the forward delay array 14 and the delay time in the delay monitor circuit 12 is set to twice the delay time of FIG. 1 (or to 2A), the internal clock signal CKxe2x80x2 is 180xc2x0 out-of-phase with the external clock signal CK.
FIG. 3 is a block diagram of a conventional SAD type clock signal generator circuit for generating an internal clock signal used to control an off-chip driver. The SAD type clock generator circuit comprises a clock control circuit 21 for generating an internal clock signal Tu synchronizing with an external clock signal CK from the external clock signal CK, a clock control circuit 22 for generating an internal clock signal Td 180xc2x0 out-of-phase with the external clock signal CK, an OR circuit 23 to which the internal clock signals Tu and Td are inputted and which generates an internal clock signal Tw, and a clock control circuit 24 for generating an internal clock signal Tx of twice the frequency of the external clock signal CK from the internal clock signal Tw.
As shown in FIG. 4, the clock control circuit 21 is composed of an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD1, and an output buffer 18 as is the circuit of FIG. 1. In the clock control circuit 21, the delay monitor circuit 12 is so set that it has the amount of delay equivalent to the sum of the signal delay time in one input buffer and that in one output buffer. Then, the clock control circuit 21 outputs an internal clock signal Tu synchronizing with the external clock signal CK.
As shown in FIG. 5, the clock control circuit 22 is composed of an input buffer 11, a delay monitor circuit 12, a SAD circuit SAD2, and an output buffer 18 as is the circuit of FIG. 1. In the clock control circuit 22, the delay monitor circuit 12 is so set that it has the amount of delay equivalent to the sum of the signal delay time in two input buffers and that in two output buffers. The number of delay circuits in the backward delay array 16 of the SAD circuit SAD2 is reduced to half the number of delay circuits in the forward delay array 14. Thus, the clock control circuit 22 outputs an internal clock signal Td 180xc2x0 out-of-phase with the external clock signal CK.
Then, when both of the internal clock signals Tu and Td are inputted to the OR circuit 23 of FIG. 3, the OR circuit 23 outputs an internal clock signal Tw of twice the frequency of the external clock signal CK. Because the internal clock signal Tw outputted from the OR circuit 23 includes the signal delay time in the OR circuit 23, it cannot be used as a control clock signal for controlling the off-chip driver.
To avoid this problem, the internal clock signal Tw outputted from the OR circuit 23 is inputted to the clock control circuit 24, which then outputs an internal clock signal Tx compensated for the signal delay time in the OR circuit 23.
The clock control circuit 24 is composed of a delay monitor circuit 12, a SAD circuit SAD3, and an output buffer 18 as shown in FIG. 6. The delay monitor circuit 12 includes an OR circuit 25 with a delay time equal to that of the OR circuit 23 and an output buffer 26 with a delay time equal to that of the output buffer 18.
The clock control circuit 24 of FIG. 6 compensates for the signal delay time in the OR circuit 23 of FIG. 3 and the signal delay time in the output buffer 28 for outputting the internal clock signal Tx and produces an internal clock signal Tx having twice the frequency of the external clock signal CK.
The internal clock signal Tx must have a great driving capability, because it is distributed to various parts of the chip. For this reason, the output buffer 18 in the clock control circuit 24 must have a large buffer capability. Therefore, to compensate for the delay time in the output buffer 18, the clock control circuit 24 using the SAD circuit of FIG. 6 is needed.
In addition, when the delay time in the OCD is large and the internal clock signal Tx must be caused to lead the external clock signal by that amount of delay, the clock control circuit 24 is also needed.
Even when each clock control circuit is in synchronization, there is an offset-error-caused synchronization error in each clock control circuit. For example, it is assumed that the SAD circuit SAD1 of FIG. 4 has a synchronization error of xcex94xcfx841 and the SAD circuit SAD2 shown in FIG. 5 has a synchronization error of xcex94xcfx842. In this case, as shown in the timing chart of FIG. 7, a synchronization error of xcex94xcfx841 occurs in the internal clock signal Tu as compared with the ideal internal clock signal Tu without a synchronization error shown by a broken line. Similarly, a synchronization error of xcex94xcfx842 occurs in the internal clock signal Td as compared with the ideal internal clock signal Td without a synchronization error shown by a broken line. Then, the internal clock signal Tw after the internal clock signals Tu and Td are ORed changes alternately in the periods of xcfx841 and xcfx842. The periods xcfx841 and xcfx842 are expressed by the following equations:
xcfx841=(1/2)xcfx84+(xcex94xcfx841xe2x88x92xcex94xcfx842)xe2x80x83xe2x80x83(2)
xcfx842=(1/2)xcfx84xe2x88x92(xcex94xcfx841xe2x88x92xcex94xcfx842)xe2x80x83xe2x80x83(3)
In a case where an attempt is made to cause the clock control circuit 24 of FIG. 6 to produce an internal clock signal Tx from the internal clock signal Tw with the period xcfx841 of FIG. 7 and the internal clock signal Tw with the period xcfx842 in the next cycle, when the SAD circuit SAD3 has no synchronization error as shown in FIG. 7, a shift in the actual internal clock signal Tx from the ideal internal clock signal Tx shown by a broken line is xe2x88x92xcex94xcfx841+2xcex94xcfx842. If the shift of xcfx841 is opposite to that of xcfx842, the difference between the actual internal clock signal Tx and the ideal internal clock signal Tx is very large.
For example, if xcex94xcfx841=xcex94xcfx84 and xcex94xcfx842=xe2x88x92xcex94xcfx84, the phase shift is tripled by the SAD circuit SAD3 to 3xcex94xcfx84, even when there is no synchronization error in the SAD circuit SAD3. If another synchronization error of xcex94xcfx84 occurs in the SAD circuit SAD3, the total error is 4xcex94xcfx84, meaning that the internal clock signal Tx has four times the synchronization error in each SAD circuit.
As described above, in the clock signal generator circuit of FIG. 3, the synchronization error is amplified by each SAD circuit. When the amplified error becomes a problem in terms of the operation of the chip, it is necessary to use a Phase Locked Loop (PLL) circuit or a Delay Locked Loop (DLL) circuit in place of the SAD circuit SAD3.
However, since the PLL circuit and DLL circuit consume more electric power and are slower in synchronous speed than the SAD circuit, the overall power consumption increases and the total synchronous speed decreases.
On the other hand, in a semiconductor integrated circuit that operates at high speed, not only the internal clock signals synchronizing with the external clock signal and having the same phase but also internal clock signals 90xc2x0 or 180xc2x0 out-of-phase with the external clock signal and an internal clock with a double period are used. Those clock signals are produced by a combination of clock control circuits.
As an example, FIG. 8 shows the configuration of a clock signal generator circuit that generates an internal clock signal Tu synchronizing with the external clock signal and an internal clock signal Td 180xc2x0 out-of-phase with the external clock signal.
In the clock signal generator circuit, a clock control circuit 31 generates an internal clock signal Tu from the external clock signal CK and a clock control circuit 32 generates an internal clock signal Td from the internal clock signal Tu.
FIGS. 4 and 9 show the configuration of the clock control circuits 31, 32 using a SAD circuit, respectively.
FIG. 9 shows a detailed configuration of the clock control circuit 32 that generates an internal clock signal Td. The clock control circuit 32 is composed of a delay monitor circuit 33, a SAD circuit SAD4 including a forward delay array 34 and a backward delay array 35, and an output buffer 36. The backward delay array 35 has half the delay time of the forward delay array 34.
In the delay monitor circuit 33, two buffers 37, 37 whose circuit configuration and circuit pattern are equivalent to those of the output buffer 36 are connected in series so that they may have the signal delay time equal to that of two units of the output buffer 36.
As described earlier, in the SAD type clock control circuit, the internal clock signal synchronizes with the external clock signal the three clocks or more after the start of the supply of the external clock signal. As a result, an asynchronous pulse signal is outputted from the clock control circuit before synchronization is established.
FIG. 10 is a timing chart to help explain an example of the operation of the clock signal generator circuit of FIG. 8 when the SAD type clock control circuit as shown in FIG. 4 or 9 is used. In FIG. 10, signal Din is the input signal to the SAD circuit SAD1 and signal Dout is the output signal from the SAD circuit SAD1.
As shown in FIG. 10, one clock control circuit 31 outputs a clock signal Tu not synchronized with the external clock signal CK as shown by C1, before the clock signal Tu (C2) synchronizing with the external clock signal CK is outputted. Because the other clock control circuit 32 starts the synchronizing operation with the internal clock signal Tu of C1, it outputs an internal clock signal Td at the position shown by C1xe2x80x2. However, since the duration between C1 and C2 is a period of xcfx84xe2x80x2, not the original period xcfx84, the clock control circuit 32 starts a synchronizing operation as if the period were xcfx84xe2x80x2.
As a result, as shown in FIG. 10, the gap between the clock signal C1xe2x80x2 generated from the clock signal C1 and the clock signal C2xe2x80x2 generated from the synchronous clock signal C2 becomes too narrow.
FIG. 10 shows the external clock signal CK when the duty is 50%, or when the high-level period is equal to the low-level period. However, when the duty of the external clock signal CK becomes high and the period of the high level becomes longer, the period of C1xe2x80x2 overlaps with that of C2xe2x80x2, with the result that the timing with which synchronization lags behind to the clock signal C3xe2x80x2 following the clock signal C2xe2x80x2.
In addition, the clock control circuit 32 outputs the asynchronous clock signal C1xe2x80x2 and other asynchronous clock signals before it outputs the synchronous clock signal C3xe2x80x2. When the internal clock signal Td is inputted to another clock control circuit, the clock control circuit also starts a synchronizing operation with the asynchronous clock signal and is therefore late in establishing synchronization.
For the above reasons, the clock signal generator circuit with more than one clock control circuit is on the whole late in establishing synchronization, even when using a high-synchronous-speed SAD type clock control circuit.
Therefore, it is necessary to operate the clock control circuit earlier than the time a synchronizing clock signal is needed or cause the clock control circuit to continue operating even when the synchronizing clock signal is unnecessary. Operating the clock control circuit in the unnecessary period increases the standby power of the entire chip, because more electric power is consumed during the period.
A first object of the present invention is to provide a clock signal generator circuit capable of reducing synchronization errors without using a PLL circuit and a DLL circuit and a semiconductor integrated circuit having the clock signal generator circuit.
A second object of the present invention is to provide a clock signal generator circuit which enables entire synchronization at high speed by providing a control circuit not outputting a clock signal until it synchronizes with an input clock signal between two clock control circuits and stops the operation in an unnecessary period, thereby preventing the standby power from increasing.
A third object of the present invention is to provide a clock signal generator circuit which enables entire synchronization at high speed by providing a configuration preventing a clock signal to be outputted until synchronization is established with an input clock signal and stops the operation in an unnecessary period, thereby preventing the standby power from increasing.
According to a first aspect of the present invention, there is provided a clock signal generator circuit comprising: an off-chip driver which has a specific signal delay time from when a control signal is inputted until it outputs data and which outputs data on the basis of the control signal; a first clock control circuit which receives a first clock signal and outputs a second clock signal synchronizing with the first clock signal and advanced in phase by at least the signal delay time in the off-chip driver; a second clock control circuit which receives a third clock signal and outputs a fourth clock signal synchronizing with the third clock signal, advanced in phase by at least the signal delay time in the off-chip driver, and having the same frequency as the second clock signal, and different in phase from the second signal; and an OR circuit which receives the second clock signal and the fourth clock signal and outputs a fifth clock signal for controlling the data output operation of the off-chip driver.
According to a second aspect of the present invention, there is provided a clock signal generator circuit comprising: an off-chip driver which outputs data on the basis of a control signal and has a different signal delay time from when the control signal is inputted until the data is outputted in outputting high-level data from the signal delay time in outputting low level data; a first control signal generator circuit which generates a first control signal inputted to the off-chip driver when the off-chip driver outputs high-level data; and a second control signal generator circuit which generates a second control signal inputted to the off-chip driver when the off-chip driver outputs low-level data.
According to a third aspect of the present invention, there is provided a clock signal generator circuit comprising: a first clock control circuit which receives a first clock signal and outputs a second clock signal; a control circuit which cuts off at least the first one of the second clock signals outputted from the first clock control circuit and thereafter sequentially outputs a group of pulse signals outputted from the first clock control circuit; and a second clock control circuit which receives the group of pulse signals outputted from the control circuit and outputs a third clock signal.
According to a fourth aspect of the present invention, there is provided a clock signal generator circuit comprising: a first clock control circuits which includes a first delay monitor circuit which receives a first clock signal, and a first synchronous adjusting delay circuit which has a first forward delay array and a first backward delay array, receives the first clock signal and the clock signal outputted from the first delay monitor circuit, causes the first forward delay array to delay, for a specific time, the clock signal outputted from the first delay monitor circuit after the input of the first clock signal in a first cycle, causes the first backward delay array to delay the first clock signal in a second cycle following the first cycle for the time equivalent to the delay time in the clock signal delayed by the first forward delay array or n/m of the delay time (where n and m are positive integers), after the first clock signal in the second cycle has arrived, and which outputs a second clock signal; a control circuit which is inserted between the input node of the first clock signal and the first synchronous adjusting delay circuit of the first clock control circuit and which cuts off at least the first one of the first clock signals and thereafter sequentially outputs the first clock signals supplied to the input node; and a second clock control circuit which receives the second clock signal from the first clock control circuit and outputs a third clock signal.
According to a fifth aspect of the present invention, there is provided a clock control circuit comprising: an input buffer which receives a clock signal; a delay monitor circuit to which the output of the input buffer is inputted and which has a specific amount of signal delay; a first delay array which is composed of a plurality of first delay circuits cascade-connected in a multistage manner and causes the cascade-connected first delay circuits to delay the output of the delay monitor circuit sequentially; a sense circuit to which the output of the delay monitor circuit is inputted and which senses a first delay circuit through which the output of the delay monitor circuit has passed in the first delay array during one period from when the delay monitor circuit outputs the clock signal in a first cycle until the clock signal in a second clock following the first cycle is outputted; a second delay array which is composed of a plurality of second delay circuits cascade-connected in a multistage manner and which causes the second delay circuit at the stage corresponding to the result of the sensing at the sense circuit to select the clock signal in the second cycle outputted from the delay monitor circuit, and sequentially delays the selected clock signal through the second delay circuits at the stages following the stage corresponding to the result; and an output buffer to which the output of the second delay array is inputted, wherein the delay monitor circuit has the amount of signal delay equivalent to the sum of the amount of signal delay in the input buffer and that in the output buffer and the second delay circuit at least the last stage in the second delay array delays only the output of the second delay circuit at the preceding stage without receiving the clock signal outputted from the delay monitor circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.